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ykurlaev/coreboot 0

github mirror of coreboot.org's master repository

starteddavidmalcolm/antipatterns.ko

started time in a day

issue commentpixelb/fslint

migrating to python3 and gtk3

Was there any progress in porting to python3 recently?

krthkj

comment created time in 3 days

startedkspalaiologos/malbolge-lisp

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PR opened pixelb/fslint

reopen stdin to /dev/null instead of just closing

stdin being closed messes up rpm subcommand when querying package list

+1 -0

0 comment

1 changed file

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PR opened pixelb/fslint

fix SUSE detection for newer openSUSE versions

openSUSE no longer use /etc/SuSE-release, grep /etc/os-release insted

+1 -1

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1 changed file

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Yaroslav Kurlaev

commit sha 5d2f9384b5d5f5e92b1a6d84cce813eea3b11e48

fix SUSE detection for newer openSUSE versions openSUSE no longer use /etc/SuSE-release, grep /etc/os-release insted

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branch : fix-rpm-stdin-issue

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branch : fix-suse-detection

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fork ykurlaev/fslint

Linux file system lint checker/cleaner

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issue commentopenSUSE/zypper

Support for exposing /var/lib/zypp/AutoInstalled

Is PR #165 related to this issue? Is there any work being done on it currently?

alexjp

comment created time in 2 months

push eventykurlaev/coreboot

Timofey Komarov

commit sha 7e7d27bf4b5b846456763c606315521548599005

soc/intel/skylake: Add microcodes for Coffee Lake CPUs The Z370, H310C and B365 PCHs use the same silicon as 200-series PCHs and they are supported by soc/intel/skylake codebase (not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired with Coffee Lake CPUs, so add the corresponding microcodes. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>

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Timofey Komarov

commit sha 756f51b66257a5af7789c06156217d6f0319b457

soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. As of the year 2021 it's common for motherboards with Z370, H310C or B365 PCHs, which are meant to be paired with Coffee Lake CPUs. Intel provides AmberLakeFspBinPkg to support this combination, which implements Intel FSP External Architecture Specification v2.1. Details: 1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and SKYLAKE_SOC_PCH_H. 2) Add Amberlake FSP support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead of KabylakeFspBinPkg. 3) Enable Coffee Lake CPUs support. If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select MAINBOARD_SUPPORTS_COFFEELAKE_CPU. 4) Increase stack and heap size in CAR. If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1), update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values. 5) Update maximal number of supported CPUs. If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16. Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>

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Kangheui Won

commit sha d8928e438b6bce4af4963eaec8a8e6b29cb32736

vendorcode: add code for cezanne psp_verstage These are mostly copied from picasso code with exception for bl_syscall_public.h. For some SVCs svc number and/or prototype has been changed. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>

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Kangheui Won

commit sha b997b0a04e758207a8db9900eb79a3f59c546193

soc/amd/cezanne: add verstage files Add support for psp_verstage compilation. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>

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Felix Singer

commit sha 38dc194485de7f13b797f125495050f673458287

soc/intel/cannonlake: Remove useless help texts Remove useless help texts since they don't add any more value. Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Felix Singer

commit sha a32a57929bb2ef1a9c5eb87d4412c486b043cfbf

soc/intel/skylake: Remove useless help texts Remove useless help texts since they don't add any more value. Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Felix Singer

commit sha edca63e796b04aa8502e88ed957202a8cd0816b0

soc/intel/cannonlake/include: Drop unused code `soc_vtd_resources` from the else-part is unused since Cannon Lake was removed. Thus, drop it and that if-else-condition. Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>

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David Wu

commit sha 0e351c9607290b72bd024ceef69afe848e0ed6d5

mb/google/dedede/var/magolor: Support VBT for Magister Default VBT supports only integrated Display port. Magister supports a HDMI port and hence support a separate VBT for Magister. BUG=b:180666608 BRANCH=dedede TEST=Build and boot to OS. Cq-Depend: chrome-internal:3661227 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I52c10452887312959f68cfc4e25d5897dae388f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51279 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Werner Zeh

commit sha 45f449416d3929a875bff76c9ee534ca9aac9dcc

mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency All the boards in the patch have a constraint for the I2C bus to operate on 100 kHz. Provide dedicated values for rise time, fall time and data hold time on mainboard level to get a proper timing which takes the bus load into account. Giving these values the driver computes the needed timings correctly. TEST=Measure I2C frequency on all boards while coreboot accesses external RTC and make sure it is 100 kHz. Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Angel Pons

commit sha 9fa141898e49a844864cfc00f1ddc4c4e1981c2a

nb/intel/haswell: Clean up haswell.h header Drop unused chipset type macros, remove unnecessary guards and reorganize contents so that headers can be included at the top. Also drop the inclusion from ASL, as it is no longer necessary. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I6fcc0d428d0fdbf410bcbeb6ae4809870b7b498f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51889 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Angel Pons

commit sha 6237175ed5ef29a0e9b82cc7268ca424c5bb44ea

nb/intel/haswell: Uniformize include guards Remove leading and trailing underscores and change `RAMINIT_H` to be more consistent with other headers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Angel Pons

commit sha 098cfd5287018ae71437d46ad5fe0272295e7377

nb/intel/common: Turn `*bar_{read,write}*` macros into functions These accessors were defined as macros in order to allow verifying the patches that replaced the accessors using BUILD_TIMELESS=1. Now that all replacement is done, turn the new accessors into static functions to let the compiler perform overflow checks on the arguments. Change-Id: Iaa2ba208fba11c4a00f2b8a05eb1129a32c6c092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52816 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Angel Pons

commit sha d6c45388a348971d15e53be760a358b0866acc07

nb/intel/haswell: Move PEG registers to a separate header To keep the "main" haswell.h header short and simple, move PEG register definitions into a separate file, as done with most other registers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ibfca00456115a4a0c861dd6738605214a7d43fd9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51891 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Angel Pons

commit sha 7e112aa7611b3511b9c7a5b2caf33bd9d0f124aa

nb/intel/common: Drop deprecated fixed BAR accessors Now that all code has been switched to make use of the new accessors, the old ones can be dropped. Follow-ups will clean up bitwise accessors. Change-Id: Ib4cb24ca71f3c3717ea50d147ddca74aaf0288fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>

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Angel Pons

commit sha 54c4ecb9f26d5913f92d3568093d9cad37b8aab6

nb/intel/common: Replace `_bar_clrsetbits_impl` macro This macro contains a cast on the and-mask, which can suppress actual type overflow issues. Replace it with wrapper functions around the existing macros in device/mmio.h which still contain a type cast, but it is a non-issue because the wrapper functions now allow compilers to check for overflows. Change-Id: I975bf8152fc961767f0292bff4a03aecd8c65f56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51886 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Tim Wawrzynczak

commit sha 13e240c60287e46feca94800d2f3302600ad0639

util/sconfig: Add support for discontiguous FW_CONFIG fields Sooner or later, some board was going to need extra FW_CONFIG bits for a field that was already in production, so this patch adds support for adding extra (unused) bits to a field. The extra are appended via a syntax like: `field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...` and the suffixed bits are all treated as if they are contiguous when defining option values. BUG=b:185190978 TEST=Modified volteer fw_config to the following: field AUDIO 8 10 | 29 29 | 31 31 option NONE 0 option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 option MAX98360_ALC5682I_I2S 5 option RT1011_ALC5682I_I2S 6 option AUDIO_FOO 7 option AUDIO_BAR 8 option AUDIO_QUUX 9 option AUDIO_BLAH1 10 option AUDIO_BLAH2 15 option AUDIO_BLAH3 16 option AUDIO_BLAH4 31 end which yielded (in static_fw_config.h): FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700 Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747 Reviewed-by: Duncan Laurie <duncan@iceblink.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Meera Ravindranath

commit sha a3f7debc89dda5cc42dbd36f64604015f22f2dbd

soc/intel/alderlake: Fill FSPM UPDs for VT-d configuration Update UPDs required for configuring VT-d. TEST=Boot to kernel, load ChromeOS VM. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51849 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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ravindr1

commit sha 745965763bb59055766a8f1a1662813387890cbb

soc/intel/alderlake: Enable HWP CPPC support in CB Kconfig change which enables the hwp cppc acpi support is to get the maximum performance of each CPU to check and enable Intel Turbo Boost Max Technology. BUG=none BRANCH=none TEST=check GCPC and CPC generated in acpi tables for each CPU Change-Id: I5d93774e8025466f1911cf77459910fe872bfcc8 Signed-off-by: ravindr1 <ravindra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51795 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Nikolai Vyssotski

commit sha 60d67ce924c48832b14487e396e6684fb9243827

soc/amd/picasso/dmi.c: Fix builds for boards without Google EC For CRBs without Google EC with CONFIG_CHROMEOS=y we will get a build error as google_chromeec_cbi_get_dram_part_num() is not defined. Use EC_GOOGLE_CHROMEEC instead of CHROMEOS to gate the call. BUG=b:184124605 Change-Id: I2b200f4fb11513c6fc17a2f0af3e12e5a3e3e5a1 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

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Maulik V Vaghela

commit sha e46e740f9155a7beeb11358b2312c3a6f6922979

mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd While building adlrvp board with chromeos.fmd and adding all chromeos related artifacts, RO region is running out of space. Also, we need to increase RW region size to accommodate all binaries and artifacts. Aligning chromeos.fmd with Brya will help in solving this issue, thus aligning chromeos.fmd with Brya. BUG=b:184997582 BRANCH=NONE TEST=Code compiles fine and able to boot adlrvp platform Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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PR opened ykurlaev/coreboot

Qemu power9
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tagexperiment-reactive

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test

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test

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Импортировать ишшуи с битбакета

https://bitbucket.org/yqy/machuchu/issues

Я не смог этого сделать.

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Yaroslav Kurlaev

commit sha 8cd3ab5cb30f578cc8a9698a4378d072c9a757c4

Initial commit

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Yaroslav Kurlaev

commit sha 6b7785ea4d5403e798566de50b12c3c312f505d0

Example shader

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Yaroslav Kurlaev

commit sha fece98831387a908e4b91c235a926cccb8c105ef

Fixed example shader

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commit sha 2ff571ac2b7e2bf53d17430d27bbbc4a2287c04c

make pygl.py executable

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commit sha 3811fa19b41d47a9f822eae67f83b11a08e6ee20

add vim modeline

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commit sha b343f7e7b2eb3a8b02a25770a9c5021c00f50da1

remove uneeded semicolons

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commit sha 476448d90d252b5914f31a9da83918466ce50807

add uniform values preservation

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Yaroslav Kurlaev

commit sha 3c5d2530382cb6c6e19fca2f9af379459a3d552a

opening shader from command line arguments

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Yaroslav Kurlaev

commit sha 2da8e7100f792d59e702b2508507583ec7fe715f

basic time handling

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Yaroslav Kurlaev

commit sha 294045341db4e03014b9a1461df09140d18f6268

not really nimbir'shtoks

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commit sha 1aee35b7226012ce14ca52e0a288cd377b9abf27

basic keyboard control

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Yaroslav Kurlaev

commit sha 11c48f942690b0cc1ac90498456f55fd90c630f3

Ascpect handling

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Yaroslav Kurlaev

commit sha f2683cd3fa33a47dd6bbb32085354aa572468816

Handle zoom and move in vertex shader

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Yaroslav Kurlaev

commit sha 5523ca17949e0c087ec49134fa80f2a7210be49b

Bugfix (#version 120)

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commit sha f9def331f456d373e2f5d3310d6d073e0ee2b419

mandelbrot_hq.f

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Yaroslav Kurlaev

commit sha 1a6fa69abff6b8277f9880c790ab49b9912cf630

Test grid shader (#version 330 required)

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Yaroslav

commit sha 2f90b4f252a40da3beebe0c827069411461bd095

Fixed (or not?) a bug

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Yaroslav

commit sha c45f6ae0c1e6cefc54da3ad53117772676812c1a

Pause (P key) feature

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Yaroslav

commit sha 974f320a1d0219c5c41a23d6617042207ad22e78

Moire shader

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Albert Safin

commit sha f428f0effa54b18d85cebdfff8c8806bd7a152ac

Show only *.f files in open dialog Do not show error message when user closes dialog

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Yaroslav Kurlaev

commit sha b19ae9dda81ba249afae1a6e77365c458528e300

A typo

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Yaroslav Kurlaev

commit sha 0784639ee65766832bb976a74512a1af9a9d174e

Tmp

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