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Junming Liu liujunming Intel Shanghai, China https://liujunming.github.io From Intel/Virtualization.

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PR opened projectacrn/acrn-hypervisor

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hv:cpuid:refine cpuid_subleaf interface

There's a corner case: When want to get CPUID.01H:EDX value, may have the following code snippet:

uint32_t unused,edx; cpuid_subleaf(0x1U, 0x0U, &unused, &unused, &unused, &edx);

while in cpuid_subleaf: *eax = leaf; *ecx = subleaf; eax and ecx point to the same location, When deep into asm_cpuid, it's input value will be 0x0U and 0x0U. but the expected input value is 0x1U and 0x0U.

This case will return CPUID.00H:EDX, which is the wrong answer.

Tracked-On: #4526

Signed-off-by: Junming Liu junming.liu@intel.com Acked-by: Eddie Dong eddie.dong@intel.com

+3 -13

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Cpu caps fixup

[External_System_ID] ACRN-5175

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hv:cpu-caps:refine is_apl_platform func and clean up duplicated code Fix the bug for "is_apl_platform" func. "monitor_cap_buggy" is identical to "is_apl_platform", so remove it. On apl platform: 1) ACRN doesn't use monitor/mwait instructions 2) ACRN disable GPU IOMMU Tracked-On:#3675 Signed-off-by: Junming Liu <junming.liu@intel.com>

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Pull request review commentprojectacrn/acrn-hypervisor

Cpu caps fixup

 bool is_apl_platform(void) { 	bool ret = false; -	if ((boot_cpu_data.displayfamily == 0x6U) && (boot_cpu_data.displaymodel == 0x92U)) {+	if ((boot_cpu_data.displayfamily == 0x6U) && (boot_cpu_data.displaymodel == 0x5c)) {

Hi, Eddie. From SDM, 06_5CH Intel Atom processors based on Goldmont Microarchitecture APL platform's DisplayModel is 0x5c, 0x92U was a bug.

I will change 0x5c -->0x5cU

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hv:cpu-caps:refine is_apl_platform func and clean up duplicated code Fix the bug for "is_apl_platform" func. "monitor_cap_buggy" is identical to "is_apl_platform", so remove it. On apl platform: 1) ACRN doesn't use monitor/mwait instructions 2) ACRN disable GPU IOMMU Tracked-On:#3675 Signed-off-by: Junming Liu <junming.liu@intel.com>

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PR opened projectacrn/acrn-hypervisor

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Cpu caps fixup
+25 -29

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PR opened projectacrn/acrn-hypervisor

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DM: PT: Add "d3hot_reset" sub-parameter for passthrough device

Some passthrough devices have no reset mechanisms which cause the device stay in unknown status during boot/reboot flow. And such unknown status cause unexpected behaviors in the guest. Except the ordinary reset mechanisms like FLR, we can utilize enter/exit D3cold as the reset that D3cold will power gate the entire hardware. But the D3cold is implemented as ACPI method which has no user interface in the SOS side. But the D3cold is implemented as ACPI method which has no user interface in the SOS side. But base on our experience, some devices can utilize D3hot instead of D3cold. But it is not useful for all PCI devices as the power status of D3hot is implementation defined. Provide one new API to program PowerState(D0/D1/D2/D3hot) in PMCSR register. Add "d3hot_reset" sub-parameter for passthrough device to enable utilize enter/exit D3hot flow to implement reset mechanisms.

Tracked-On: #5067

Signed-off-by: Long Liu long.liu@intel.com Reviewed-by: Yuan Liu yuan1.liu@intel.com Acked-by: Yu Wang yu1.wang@intel.com

+36 -1

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