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Emil Fresk korken89 Sweden PhD in Robotics, embedded Rust nerd, and machine vision hardware/software designer from Sweden. Co-founder of WideFind AB.

japaric/heapless 547

Heapless, `static` friendly data structures

korken89/crect 158

A C++, compile-time, reactive RTOS for the Stack Resource Policy based Real-Time For the Masses kernel

alphaville/optimization-engine 148

Nonconvex embedded optimization: code generation for fast real-time optimization

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A Rust library for digital second order IIR filtrers, also known as biquads

japaric/vcell 13

Just like `Cell` but with volatile read / write operations

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Matlab code to let information be easily plotted with tikz

PR merged rust-embedded/cortex-m-rt

Forward-port v0.6.12/13 changelog S-waiting-on-review T-cortex-m

Fixes https://github.com/rust-embedded/cortex-m-rt/issues/299

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Merge #309 309: Forward-port v0.6.12/13 changelog r=adamgreig a=jonas-schievink Fixes https://github.com/rust-embedded/cortex-m-rt/issues/299 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

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Forward-port Changelog entries for v0.6.x

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Merge #309 309: Forward-port v0.6.12/13 changelog r=adamgreig a=jonas-schievink Fixes https://github.com/rust-embedded/cortex-m-rt/issues/299 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

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pull request commentrust-embedded/cortex-m-rt

Forward-port v0.6.12/13 changelog

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PR opened rust-embedded/cortex-m-rt

Forward-port v0.6.12/13 changelog

Fixes https://github.com/rust-embedded/cortex-m-rt/issues/299

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PR merged rust-embedded/cortex-m

Backport changelog from 0.6.x S-waiting-on-review T-cortex-m
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Backport changelog from 0.6.x

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commit sha c714cdf20e012280a5c722d190a121a6bce10ddc

Merge #323 323: Backport changelog from 0.6.x r=therealprof a=adamgreig Co-authored-by: Adam Greig <adam@adamgreig.com>

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pull request commentrust-embedded/cortex-m

Backport changelog from 0.6.x

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Hugues de Valon

commit sha 41d88439174234bad109d0c04d6c8a352b23497b

Add Security Attribution Unit support The SAU is a Armv8-M core peripheral that, alongside the Implementation Defined Attribution Unit, manages the security attribution of the memory zones. This driver provides abstraction to help setting the SAU up. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>

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Jonas Schievink

commit sha 0a668e4181b9bb3df3da2d5c720e3b520dfa6713

Remove `aligned`, improve ITM code

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Jonas Schievink

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Fix typo

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bors[bot]

commit sha 465c64dca26b3fbd8137720b1d24b13d56c5d5d8

Merge #190 190: Remove `aligned`, improve ITM code r=adamgreig a=jonas-schievink This does a handful of things: * Removes the dependency on `aligned` (and thus `as-slice` and the 2 versions of `generic-array`), instead providing our own simplified `Aligned` wrapper * Moves the innards of `write_aligned` to its own function, and calls that from `write_all` instead of transmuting `&[u8]` to `&Aligned<A4, [u8]>` (which is likely UB) * Fixes the doc example, which didn't compile anymore * Sinks the `#[allow]` attributes into the functions so they only cover the statements they need to Closes https://github.com/rust-embedded/cortex-m/issues/184 Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

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Jonas Schievink

commit sha ab8d4634fa34881a97f4c15bb0ecbde946c4107f

Remove deprecated APIs and the `const-fn` feature

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commit sha 22d47dd75e9fb5004e0192666123d28f0a418310

Merge #191 191: Remove deprecated APIs and the `const-fn` feature r=adamgreig a=jonas-schievink Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

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Adam Greig

commit sha 4b4f825f4fbf3ffca1e7eedc363f4f005de6fed3

Update and improve cache operations. Closes #47, #188. Breaking change due to changing safety of d-cache invalidation functions.

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Jonas Schievink

commit sha 34f47ddba972e5f697392d30a6c302e93bb0502c

Clean up the doc examples in `peripheral` The Clippy lint was unnecessarily `#[allow]`ed.

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Jonas Schievink

commit sha 6e63b1e9b94bc08b8cd84383c51b93f6170eb594

Make `Peripherals` `#[non_exhaustive]`

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Jonas Schievink

commit sha d44a5fa86a75a97acef5321d2e061a914cf8d871

Use a private field instead of `#[non_exhaustive]`

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Adam Greig

commit sha 9fac3d9f4c598c5a0929dcae0e62a486e247d021

Update documentation for cache functions; use dynamic cache line size

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Adam Greig

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Apply suggestions from code review Co-Authored-By: Jonas Schievink <jonasschievink@gmail.com>

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Adam Greig

commit sha 9ad4e10d8a96b283b31b3309a65678513d50e270

Add missing inline(always) and change more initialised->initialized

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bors[bot]

commit sha 319773eaf338cbf7d1380611ba62f5a1dbfa3094

Merge #192 192: Update and improve cache operations. r=jonas-schievink a=adamgreig Closes #47, #188. I've implemented the proposed methods from #47 and marked all d-cache invalidation functions as unsafe. It's not unsafe to invalidate i-cache or branch predictor as they are read-only caches. The clean and clean+invalidate operations do not alter memory from the executing core's point of view so are also safe. It wasn't possible to remove the requirement to pass in `&mut CPUID` as you require synchronized access to `CPUID` to read the number of sets and ways in the cache, which is required to fully clean or invalidate them, which is required to enable or disable them. So it goes. Breaking change due to changing safety of d-cache invalidation functions. Co-authored-by: Adam Greig <adam@adamgreig.com>

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Hugues de Valon

commit sha 426ef1132f23b96103276020a4026b18fc8b0a71

Remove unnecessary parenthesis Otherwise Cargo complains! Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>

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commit sha 947714ee4dac6629e4e286ea49b7822b0702575b

Merge #198 198: Remove unnecessary parenthesis r=jonas-schievink a=hug-dev Otherwise Cargo complains! This should fix the CI for #193 and #189 Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>

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commit sha 72befe4c163e59393789d3043afe1e67a7fc0044

Merge #193 193: Make `Peripherals` non-exhaustive and improve its docs r=therealprof a=jonas-schievink This means that it's no longer a breaking change to add fields to it, which is important since Arm is likely to add more in upcoming architectures. They could also add extensions that add peripherals. Co-authored-by: Jonas Schievink <jonasschievink@gmail.com>

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Hugues de Valon

commit sha 2bbfd8c976fed21e24865618b0a9975d9ab542c4

Initial Rust CMSE support Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added cmse module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>

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Hugues de Valon

commit sha 2433d85190dad9e4cbaa4086eba796ab59bf0adb

Allow clippy::match_single_binding Clippy complains that the match expressions used for cfg gating could be rewritten as a let statement, this is a false positive. Also adds inline on two functions. Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>

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commit sha 1cb6baf8bd46b602c01d51e7a3c5c6e77af9c8f2

Merge #189 189: Initial Rust CMSE support r=thejpster a=hug-dev Armv8-M and Armv8.1-M architecture profiles have an optional Security Extension which provides a set of Security features. This patch adds initial support of the Cortex-M Security Extensions but providing support for the TT intrinsics and helper functions on top of it in the newly added `cmse` module of this crate. The code is a Rust idiomatic implementation of the C requirements described in this document: https://developer.arm.com/docs/ecm0359818/latest Executed `assemble.sh` to generate the new static libraries containing the `TT*` instructions. Tested `check_blobs.sh` locally and it passed. Tested on QEMU using the `mps2-an505` machine. Co-authored-by: Hugues de Valon <hugues.devalon@arm.com>

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Backport changelog from 0.6.x

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pull request commentrust-embedded/cortex-m

Fix missing peripheral::itm export, prepare v0.6.7

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pull request commentrust-embedded/cortex-m

Backport changelog from 0.6.x

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PR opened rust-embedded/cortex-m

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Low level access to Cortex-M processors

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PR merged rust-embedded/cortex-m

Fix missing peripheral::itm export, prepare v0.6.7 S-waiting-on-review T-cortex-m

This fixes the issue where cortex-m 0.5.10 re-exports 0.6's peripheral::itm module; in principle it's possible other crates could have been using this module directly too (it is public) but in practice it doesn't contain anything useful (all the useful things are in the top-level itm module).

Should fix https://github.com/rust-embedded/discovery/issues/287.

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Fix missing peripheral::itm export, prepare v0.6.7

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Merge #322 322: Fix missing peripheral::itm export, prepare v0.6.7 r=jonas-schievink a=adamgreig This fixes the issue where cortex-m 0.5.10 re-exports 0.6's peripheral::itm module; in principle it's possible other crates could have been using this module directly too (it is public) but in practice it doesn't contain anything useful (all the useful things are in the top-level itm module). Should fix https://github.com/rust-embedded/discovery/issues/287. Co-authored-by: Adam Greig <adam@adamgreig.com>

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Fix missing peripheral::itm export, prepare v0.6.7

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Merge #322 322: Fix missing peripheral::itm export, prepare v0.6.7 r=jonas-schievink a=adamgreig This fixes the issue where cortex-m 0.5.10 re-exports 0.6's peripheral::itm module; in principle it's possible other crates could have been using this module directly too (it is public) but in practice it doesn't contain anything useful (all the useful things are in the top-level itm module). Should fix https://github.com/rust-embedded/discovery/issues/287. Co-authored-by: Adam Greig <adam@adamgreig.com>

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